In a main stream CMOS or BiCMOS process a PWELL/pwell in an NMOS can be implanted in a P/p-type substrate and thereby the biasing of the pwell is common for all the NMOS transistors on a chip. In order to prevent a global biasing, a TRIPLE WELL/triple well option can be used. The use of a triple well is earlier known and a method to provide a triple well has been earlier published, see e.g. U.S. Pat. No. 6,388,295 and Japanese Patent No. 11026601.
The use of a triple well firstly provides an opportunity to have a separate biasing on each NMOS transistor and hence adjust a threshold voltage individually. For an analogue RF and perhaps most desirably for mixed signals circuits the use of a triple well also isolates the NMOS transistors and suppresses noise couplings. There are several benefits, which can be achieved by using a triple well concept. In an integrated circuit a global biasing for a group of transistors can be of advantage.